`include "../define.svh"
//经过非规格舍入模块处理，略去了下溢出处理的部分
module overflow (
    input [1:0]data_type,
    input [23:0]m_norm_i,
    input [9:0]e_norm_i,
    output reg [7:0]e_out_final,
    output [23:0]m_out_final
);
    assign overflow = (data_type==`FP16) ? (e_norm_i>10'b0000011110):(e_norm_i>10'b0011111110); //溢出标志
    //assign underflow = (data_type[1]) ? (e_norm_i<10'sd0000000001):(1'b0);

    assign m_out_final = (overflow) ? (24'd0): (m_norm_i);
    always @(*) begin
       if (overflow) begin
        case (data_type)
            `FP16: e_out_final=`FP16_INF_EXP;
            `FP32: e_out_final=`FP32_INF_EXP;
            default: e_out_final=8'd0;
        endcase
       end 
       else e_out_final=e_norm_i[7:0];
    end
    
endmodule